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| - 스위스 로잔연방공대에서 2013 년, 2015 년, 2018 년에 각각 학사, 석사, 박사학위 취득 - 2016 년~2018 년: IBM 리서치 취리히연구소 방문연구원 - 2018 년~2020 년: KAIST 박사후연구원 - 2020 년~2022 년: 삼성리서치 근무 - 2022 년~현재: DGIST 조교수 |
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| Ever-increasing demands for higher I/O bandwidth in network infrastructures and data centers have been motivating the high-speed SerDes to increase its per-lane data rate by a factor of two every four years. With the increasing data rate to 112Gb/s per lane, PAM-4 with ADC-DSP-based RX has become the most commonly employed modulation and RX architecture for ultra-high-speed SerDes. Network switch SoCs now support 51.2Tb/s with 100Gb/s PAM-4 SerDes, maintaining the same pin counts. However, while the SerDes data rate keeps increasing over the years, the energy efficiency of the link does not improve at the same rate. This talk overviews recent advances of SerDes in various applications, underlying challenges and introduces emerging SerDes architectures beyond PAM-4. | |||||||||||||||||
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